Digital filtering and in particular, digital processing of analog signals (A/D conversion) is now well known. The processing of analog signals can be done much more efficiently with digital methods than with analog methods. Better signal-to-distortion and signal-to-noise ratios, faster design cycles, and lower product cost are some benefits of A/D conversion.
Any form or method of A/D conversion consists of at least two operations. The first operation is sampling and the second is signal quantization.
Sampling consists of taking samples of the analog signal at regular intervals while quantization involves assigning a digital value to the sampled analog signal. During quantization, it is desirable to limit the number of different values that the samples can assume so that each sample can be expressed as a digital word with a finite number of bits.
Various analog sampling and conversion to a digital bit stream methods have been developed. One popular method, commonly referred to as the Delta-Sigma method (sometimes also referred to as Sigma-Delta), was developed in the 1960's in an attempt to provide highly accurate low frequency A/D converters. See for example, "A Unity Bit Coding Method by Negative Feedback", by H. Inose and Y. Yasuda, Proceedings of the IEEE, November 1963.
Utilizing the Delta-Sigma method, an effective and efficient filter can be provided using digital filter circuits which incorporate one or more digital multipliers and digital adders. Although the digital multipliers and digital adders contribute to the effectiveness of a digital filter, adders, and especially multipliers also contribute to the large size and power consumption of such digital filter circuits.
Additionally, it is often desired to provide an A/D converter in which the filter rate can be adjusted to suit the needs of the application or which can be dynamically adjusted, as desired, in real time. Such filters typically require either multiple digital filter stages designed and laid out on the same semiconductor chip, or a single digital filter stage incorporating a multiplier and adder which can be utilized for each "stage" of filtering by utilizing stored filter coefficients. Each "set" of filter coefficients is designed to provide a specific decimation rate and filter transfer function.
Some prior art attempts have been made at providing a multiplierless digital filter. Multipliers in a single bit digital Delta-Sigma filter can be eliminated if all the filtering is performed in one stage (the multiplicand is 1 or 0 and therefore the operation is really an addition). Such single stage multiplierless filters, however, cannot perform variable decimation filtering without storing separate coefficients for each filter in ROM.
When implementing a multi-stage filter with several coefficient sets, the length of the filter and the size of the ROM required to store the coefficient sets can become quite large, although not as large as the size of a multiplier. For example, for an 8 (eight) stage single bit filter, approximately 200,000 (200K) bits of ROM are required. Most importantly, however, filter efficiency including filter rate, power dissipation and frequency response is greatly affected when the filter circuit length is increased and when the filter must continuously access ROM to retrieve different coefficient sets.
Although complicated and highly efficient filters are desirable, modern technology is driving the size and power consumption of integrated circuits to their limits and dictating that highly efficient dc accurate multi-rate or variable decimation digital filters must be provided in considerably less size or area on the silicon, and with greatly reduced power consumption.